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 NLX2G00 Dual 2-Input NAND Gate
The NLX2G00 is an advanced high-speed dual 2-input CMOS NAND gate in ultra-small footprint. The NLX2G00 input structures provide protection when voltages up to 7.0 volts are applied, regardless of the supply voltage.
Features http://onsemi.com MARKING DIAGRAMS
ULLGA8 1.45 x 1.0 CASE 613AA ULLGA8 1.6 x 1.0 CASE 613AB ULLGA8 1.95 x 1.0 CASE 613AC XX M G QM G
* * * * * * *
High Speed: tPD 2.4 ns (typical) at VCC = 5.0 V Designed for 1.65 V to 5.5 V VCC Operation Low Power Dissipation: ICC = 1 mA (Max) at TA = 25C 24 mA Balanced Output Sink and Source Capability Balanced Propagation Delays Overvoltage Tolerant (OVT) Input Pins This is a Pb-Free Device
1
1
AJM G
A1
1
8
VCC
1
AHM G
= Specific Device Code = Date Code = Pb-Free Package
B1
2
7
Y1
PIN ASSIGNMENT
Pin Function A1 B1 Y2 GND A2 B2 Y1 VCC 1 2 3
Y2
3
6
B2
GND
4
5
A2
4 5
Figure 1. Pinout
6 7
IEEE/IEC A1 B1 A2 B2 & Y1 Y2 A
8
FUNCTION TABLE
Y = AB Inputs B L H L H Output Y H H H L
Figure 2. Logic Symbol
L L H H
H = HIGH Logic Level L = LOW Logic Level
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2009
December, 2009 - Rev. 0
1
Publication Order Number: NLX2G00/D
NLX2G00
MAXIMUM RATINGS
Symbol VCC VIN VOUT IIK IOK IO ICC IGND TSTG TL TJ qJA PD MSL FR VESD DC Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Source/Sink Current DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Range Lead Temperature, 1 mm from Case for 10 Seconds Junction Temperature Under Bias Thermal Resistance (Note 1) Power Dissipation in Still Air at 85C Moisture Sensitivity Flammability Rating ESD Withstand Voltage Oxygen Index: 28 to 34 Human Body Model (Note 2) Machine Model (Note 3) Charged Device Model (Note 4) (Note 5) VIN < GND VOUT < GND Parameter Value *0.5 to +7.0 *0.5 to +7.0 *0.5 to VCC + 0.5 *50 *50 $50 $100 $100 *65 to )150 TBD TBD TBD TBD Level 1 UL 94 V-0 @ 0.125 in > 2000 > 200 N/A $500 V Unit V V V mA mA mA mA mA C C C C/W mW
ILatchup
Latchup Performance Above VCC and Below GND at 125C
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Measured with minimum pad spacing on an FR4 board, using 10 mm-by-1 inch, 2-ounce copper trace with no air flow. 2. Tested to EIA/JESD22-A114-A. 3. Tested to EIA/JESD22-A115-A. 4. Tested to JESD22-C101-A. 5. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VIN VOUT TA Dt/DV Power DC Supply Voltage Digital Input Voltage (Note 6) Output Voltage Operating Free-Air Temperature Input Transition Rise or Fall Rate VCC = 1.8 V $0.15 V VCC = 2.5 V $0.2 V VCC = 3.3 V $0.3 V VCC = 5.0 V $0.5 V Parameter Operating Data Retention Only Min 1.65 1.5 0 0 -55 0 0 0 0 Max 5.5 5.5 5.5 VCC +125 20 20 10 5 Unit V V V C ns/V
6. Unused inputs may not be left open. All inputs must be tied to a high- or low-logic input voltage level.
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2
NLX2G00
DC ELECTRICAL CHARACTERISTICS
VCC (V) 1.65 2.3 to 5.5 1.65 2.3 to 5.5 VIN = VIH or VIL, IOH = -100 mA VIN = VIH or VIL IOH = -4 mA IOH = -8 mA IOH = -12 mA IOH = -16 mA IOH = -24 mA IOH = -32 mA VOL Low-Level Output Voltage VIN = VIH or VIL, IOL = 100 mA VIN = VIH or VIL IOL = 4 mA IOL = 8 mA IOL = 12 mA IOL = 16 mA IOL = 24 mA IOL = 32 mA IIN IOFF ICC Input Leakage Current Power-Off Input Leakage Current Quiescent Supply Current 0 VIN 5.5 V VIN = 5.5 V 0 VIN 5.5 V 1.65 to 5.5 VCC - 0.1 1.29 1.9 2.2 2.4 2.3 3.8 VCC TA = 255C Min 0.75 x VCC 0.7 x VCC 0.25 x VCC 0.3 x VCC VCC - 0.1 1.29 1.9 2.2 2.4 2.3 3.8 0.1 0.1 Typ Max TA 3 855C Min 0.75 x VCC 0.7 x VCC 0.25 x VCC 0.3 x VCC VCC - 0.1 1.29 1.9 2.2 2.4 2.3 3.8 0.1 V Max TA = -555C to +1255C Min 0.75 x VCC 0.7 x VCC 0.25 x VCC 0.3 x VCC Max Unit V
Symbol VIH
Parameter High-Level Input Voltage
Condition
VIL
Low-Level Input Voltage
V
VOH
High-Level Output Voltage
V
1.65 2.3 2.7 3.0 3.0 4.5 1.65 to 5.5
1.5 2.1 2.4 2.7 2.5 4.0
1.65 2.3 2.7 3.0 3.0 4.5 0 to 5.5 0 5.5
0.08 0.20 0.22 0.28 0.38 0.42
0.24 0.3 0.4 0.4 0.55 0.55 $0.1 1.0 1.0
0.24 0.3 0.4 0.4 0.55 0.55 $1.0 10 10
0.24 0.3 0.4 0.4 0.55 0.55 $1.0 10 10 mA mA mA
AC ELECTRICAL CHARACTERISTICS tR = tF = 2.5 ns
VCC Symbol tPLH tPHL Parameter Propagation Delay Input A to Output (V) 1.65 to 1.95 2.3 to 2.7 3.0 to 3.6 Test Condition RL = 1 MW, CL = 15 pF RL = 1 MW, CL = 15 pF RL = 1 MW, CL = 15 pF RL = 500 W, CL = 50 pF 4.5 to 5.5 RL = 1 MW, CL = 15 pF RL = 500 W, CL = 50 pF CIN CPD Input Capacitance Power Dissipation Capacitance (Note 7) 5.5 3.3 5.5 VIN = 0 V or VCC 10 MHz, VIN = 0V or VCC Min 2.0 1.2 0.8 1.2 0.5 0.8 TA = 255C Typ 5.7 3.2 2.4 3.0 1.9 2.4 2.5 9 11 Max 10.5 5.3 3.7 4.6 2.9 3.6 TA 3 855C Min 2.0 1.2 0.8 1.2 0.5 0.8 Max 11.0 5.7 4.0 4.9 3.2 3.9 TA = -555C to +1255C Min TBD TBD TBD TBD TBD TBD Max TBD TBD TBD TBD TBD TBD pF pF Unit ns
7. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC. CPD is used to determine the no-load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
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3
NLX2G00
tf = 3 ns
90% 50% 10% 90% 50% 10%
tf = 3 ns VCC VCC OUTPUT CL tPHL tPLH VOH A 1-MHz square input wave is recommended for propagation delay tests. VOL
INPUT A and B
GND
INPUT
OUTPUT Y
50%
50%
Figure 3. Switching Waveform
Figure 4. Test Circuit
ORDERING INFORMATION
Device NLX2G00AMX1TCG NLX2G00BMX1TCG NLX2G00CMX1TCG Package ULLGA8, 1.95 x 1.0, 0.5P (Pb-Free) ULLGA8, 1.6 x 1.0, 0.4P (Pb-Free) ULLGA8, 1.45 x 1.0, 0.35P (Pb-Free) Shipping 3000 / Tape & Reel 3000 / Tape & Reel 3000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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4
NLX2G00
PACKAGE DIMENSIONS
ULLGA8 1.45x1.0, 0.35P CASE 613AA-01 ISSUE A
D A B
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 mm FROM THE TERMINAL TIP. 4. A MAXIMUM OF 0.05 PULL BACK OF THE PLATED TERMINAL FROM THE EDGE OF THE PACKAGE IS ALLOWED. DIM A A1 b D E e L L1 SEATING PLANE MILLIMETERS MIN MAX --- 0.40 0.00 0.05 0.15 0.25 1.45 BSC 1.00 BSC 0.35 BSC 0.25 0.35 0.30 0.40
PIN ONE REFERENCE
0.10 C
0.10 C 0.05 C
8X
0.05 C
e/2 e
1 4 7X
L1 1
PKG OUTLINE
EEE EEE EEE
8
E
TOP VIEW
A SIDE VIEW A1 C
MOUNTING FOOTPRINT SOLDERMASK DEFINED*
0.48
7X
0.22
8X
L
NOTE 4
1.18
0.53
5 8X
b 0.10 C A B 0.05 C
NOTE 3
0.35 PITCH
DIMENSIONS: MILLIMETERS
BOTTOM VIEW
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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5
NLX2G00
PACKAGE DIMENSIONS
ULLGA8 1.6x1.0, 0.4P CASE 613AB-01 ISSUE A
D A B
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 mm FROM THE TERMINAL TIP. 4. A MAXIMUM OF 0.05 PULL BACK OF THE PLATED TERMINAL FROM THE EDGE OF THE PACKAGE IS ALLOWED. DIM A A1 b D E e L L1 SEATING PLANE MILLIMETERS MIN MAX --- 0.40 0.00 0.05 0.15 0.25 1.60 BSC 1.00 BSC 0.40 BSC 0.25 0.35 0.30 0.40
PIN ONE REFERENCE
0.10 C 0.10 C 0.05 C
8X
0.05 C
e/2 e
1 4 7X
L1 1
PKG OUTLINE
EEE EEE EEE
8
E
TOP VIEW
A SIDE VIEW A1 C
MOUNTING FOOTPRINT SOLDERMASK DEFINED*
0.49
7X
0.26
8X
L
NOTE 4
1.24
0.53
5 8X
b 0.10 C A B 0.05 C
NOTE 3
0.40 PITCH
DIMENSIONS: MILLIMETERS
BOTTOM VIEW
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
6
NLX2G00
PACKAGE DIMENSIONS
ULLGA8 1.95x1.0, 0.5P CASE 613AC-01 ISSUE A
D A B
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 mm FROM THE TERMINAL TIP. 4. A MAXIMUM OF 0.05 PULL BACK OF THE PLATED TERMINAL FROM THE EDGE OF THE PACKAGE IS ALLOWED. DIM A A1 b D E e L L1 MILLIMETERS MIN MAX --- 0.40 0.00 0.05 0.15 0.25 1.95 BSC 1.00 BSC 0.50 BSC 0.25 0.35 0.30 0.40
PIN ONE REFERENCE
0.10 C
0.10 C 0.05 C
8X
0.05 C
L1 1
PKG OUTLINE
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
EEEE EEEE EEEE
e/2
1 8
E
TOP VIEW
A SIDE VIEW A1 C
SEATING PLANE
MOUNTING FOOTPRINT SOLDERMASK DEFINED*
0.49
7X
0.30
8X
e
4
7X
L
NOTE 4
1.24
0.53
5 8X
b 0.10 C A B 0.05 C
NOTE 3
0.50 PITCH
DIMENSIONS: MILLIMETERS
BOTTOM VIEW
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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7
NLX2G00/D


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